Spin-torque magnetic memory devices store information by controlling the resistance across a magnetic tunnel junction (MTJ) such that a read current through the magnetic tunnel junction results in a voltage drop having a magnitude that is based on the state of the magnetoresistive stack. The resistance in each magnetic tunnel junction can be varied based on the relative magnetic states of the magnetoresistive layers within the magnetoresistive stack. In such memory devices, there is typically a portion of magnetoresistive stack that has a fixed magnetic state and another portion that has a free magnetic state that is controlled to be either one of two possible states relative to the portion having the fixed magnetic state. Because the resistance through the magnetic tunnel junction changes based on the orientation of the free portion relative to the fixed portion, information can be stored by setting the orientation of the free portion. The information is later retrieved by sensing the orientation of the free portion. Such magnetic memory devices are well known in the art.
Writing to magnetic memory cells can be accomplished by sending a spin-polarized write current through the memory cell where the angular momentum carried by the spin-polarized current can change the magnetic state of the free portion of the magnetic tunnel junction. One of ordinary skill in the art understands that such a current can either be directly driven through the memory cell or can be the result of applying one or more voltages, where the applied voltages result in the desired current. Depending on the direction of the current through the memory cell, the resulting magnetization of the free portion will either be parallel or antiparallel to the fixed portion. If the parallel orientation represents a logic “0”, the antiparallel orientation represents a logic “1”, or vice versa. Thus, the direction of write current flow through the memory cell determines whether the memory cell is written to a first state or a second state. In such memories, the magnitude of the write current is typically greater than the magnitude of a read current used to sense the information stored in the memory cells.
Each memory cell often includes a magnetic tunnel junction coupled in series with a corresponding selection transistor that allows each memory cell to be individually selected for access. In some architectures, each memory cell is coupled between two common lines, which are often referred to as a bit line and a source line. A memory array typically includes many bit lines and source lines that allow selective access to subsets of the memory cells within the array. Word lines are coupled to the gates of the selection transistors, thereby controlling current flow through the series circuit of each memory cell based on the voltages applied to the ends of the magnetic memory cell by, for example, the bit lines and source lines.
Because a magnetic random access memory (“MRAM”) may include thousands or millions of memory cells, reducing the amount of area needed for each memory cell and the associated access circuitry for the memory cell can provide for increased memory cell density. Higher memory cell density allows for greater data storage capacity in the MRAM. Therefore, it is desirable to provide access circuitry for MRAMs that efficiently enables memory operations with minimal area requirements.